Researchers from Google and Delft University of Technology published a technical paper titled “Innovative FA Hardware Solution to Enable System-Level Debug of 3D ICs.”
Abstract Excerpt: “This paper presents a novel Failure Analysis (FA) hardware and sample preparation solution that enables System-Level FA on mobile System-on-a-Chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing EFI on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called Through Interposer Vias (TIVs). For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon, utilizing the smallest possible interposer pin pitch (∼210 um) and advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications. ”
Find the technical paper here. 2026.
Endrinal, Lesly, Jehan Saujauddin, YuanChung Ho, Dilbagh Singh, Sasi Sekaran Sundaresan, Vinod Kumar Kakumanu, Jessen Gonzalez, Willem D. van Driel, and G. Q. Zhang. “Innovative FA hardware solution to enable system-level debug of 3D ICs.” Microelectronics Reliability 184 (2026): 116230. Creative Commons license.